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Ishikura, Keisuke,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ito, Takuma Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.4
Parallel operation systems have an advantage in that they can be constructed quickly and inexpensively by combining existing electric power converters. However, in this case, there is a peculiar problem in that a cross current flows between the electric power converters. To design a control system more simply and commonalize the core of combination reactors, we reviewed a system construction method for parallel operation systems constructed with three electric power converters.
Method Controlling Two or More Sets of PMSM by One Inverter on a Railway Vehicle
Ito, Takuma,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.2
If two or more Permanent Magnet Synchronous Motors (PMSM) can be controlled by one inverter, a train can be driven by less energy than the present Induction Motor (IM) drive system. First, this paper proposes a method for simulating the movement of wheels and a vehicle to develop a control method. Next, a method is presented for controlling two or more PMSMs by one inverter.
Ito, Takuma,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.4
If it were possible to control four sets of PMSMs in place of induction motors by using one inverter, we could attain efficient driving trains. In this paper, a method for controlling three sets of PMSMs with one inverter is shown. Additionally, this shows the method to control four sets of PMSMs with one inverter and the results of a simulation with the proposed method.
Parallel Multiple Electric Power Conversion System Constructed by Connecting Three Power Converters
Nakai, Mitsuki,Inaba, Hiromi,Kishine, Keiji,Ishikura, Keisuke Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.3
The electric power conversion system constructed by connecting two or more power converters in parallel is an advantageous method for making to large capacity and standardization. In this paper, the control method of cross current when three power converters are operated is examined, and it reexamined a preferable system construction method.
Ishikura, Keisuke,Inaba, Hiromi,Kishine, Keiji,Nakai, Mitsuki,Ito, Takuma Journal of International Conference on Electrical 2014 Journal of international Conference on Electrical Vol.3 No.3
A large capacity power conversion system constructed by using two or more existing power converters has a lot of flexibility in how the power converters are used. However, at the same time, it has a problem of cross current flows between power converters. The cross current must be suppressed by controlling the system while miniaturizing the combination reactor. This paper focuses on two current control methods of a power conversion system constructed by using two power converters connected in parallel supplying the same power. In order to elucidate the control performance of cross current, each control method which are aimed at controlling cross current and not directly controlling it are examined in simulations.
Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique
Daichi Omoto,Keiji Kishine,Hiromi Inaba,Tomoki Tanaka 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.3
This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the “labeling signal” in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.
Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS
Kosuke Furuichi,Hiromu Uemura,Natsuyuki Koda,Hiromi Inaba,Keiji Kishine 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper describes a method of designing a circuit to detect high-linearity delay at 10 Gb/s. We proposed a transmission system for additional data in previous work, by using a frequency modulation technique. The demodulation characteristics in the receiver strongly depended on data speed. As the data speed gets higher, demodulation characteristics linearity degradation become larger. In this paper, we propose a circuit to provide high-linearity demodulation characteristics by using an emphasis technique which reduces degradation in the demodulated signal. We fabricated the circuit to detect delay with an emphasis technique by using 65- nm CMOS process. The results we obtained from measurements, revealed an integrated circuit (IC) achieved 10% higher linearity than a receiver without emphasis at 10 Gb/s.
10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS
Hiromu Uemura,Kosuke Furuichi,Natsuyuki Koda,Hiromi Inaba,Keiji Kishine 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2
Currently, there is a great demand for high speed and large capacity communication systems. Therefore, it is important to develop circuit and device technologies that support these systems. Furthermore, it is important that high speed and large capacity systems are developed based on those technologies. In this paper, we propose a transmitter design method for the transmission system that the additional signal add to 10-Gb/s signal. The system transmits the data frames and the additional information simultaneously. To add the additional information, called the "labeling signal", to the data frames, we perform a frequency modulation technique on the transmitted data frames. To confirm the performance of the proposed circuit and design method, we fabricate an IC with the proposed system’s transmitter by using the 65-nm CMOS process. We confirm that the data frames are frequency modulated and the transmitter generates the frequency-modulated data frames.
Natsuyuki Koda,Furuichi Kosuke,Hiromu Uemura,Hiromi Inaba,Keiji Kishine 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper proposes a simple and low power highly sensitive frequency demodulator. In the previous work, we proposed a multiplex communication system that transmits additional data by using a frequency modulation technique and the proposed circuit provided highly sensitive characteristics on frequency demodulation. However, with this configuration, there is the problem that the power consumption and the number of control points increase. Therefore, in this paper, we propose a simple and lower power circuit configuration. We investigated the characteristics of these frequency demodulators using a prototype demodulation system consisting of an FPGA and discrete devices. Compared with the delay detection circuit, the proposed simple and lower power demodulation system, which showed the same output characteristics as the conventional sensitive demodulator, successfully detected about twice the detection data than the delay detection circuit did.
A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-㎚ CMOS
Tomoki Tanaka,Keiji Kishine,Akira Tsuchiya,Hiromi Inaba,Daichi Omoto 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.3
Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-㎚ CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.