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저전압/고용량 DRAM 회로를 위한 Half-VDD 전압 발생기 설계
이재형,우엄찬,박무훈,최중경,하판봉,김영희 국립7개대학공동논문집간행위원회 2005 공업기술연구 Vol.5 No.-
A half-VDD voltage generator(VHDD) using PMOS pull-up and NMOS pull-down transistors, and each of the gate voltage is able to swing at CMOS voltage level was newly proposed. Designed with these, pull-up current was made to be proportional to (VDD-|V_(TP)|)^2 and pull-down current was made to be proportional to (VDD-|V_(TN)|)^2. Also, being turned on pull-up and pull-down transistors at the same time was prevented by using short-circuit current protection circuit. Test chips which were designed by using 0.35μm CMOS twin-well process technology were fabricated and the result of measurement was suitable for low-boltage DRAMs.