영남문집해제 : 성재집 (省齋集) ( 손윤구 )

손윤구 영남대학교 민족문화연구소 1988 민족문화연구소 자료총서 Vol.4 No.-

高信賴性 計數回路 設計에 關한 硏究

孫潤求 영남대학교 공업기술연구소 1985 연구보고 Vol.13 No.2

As the (7,3) cyclic code is applied to the design of the counter, unit block is a three-bit count module with four redundant bits. Thus the proposed implementation is an approach for realizing the modular LSI of sequential circuit with high information rate. More than three-bit circuit realization is attainable by connecting three-bit count modules in cascade. In this paper, a synthesis procedure for realizing a single-failure-tolerant parallel binary counter with double-failure-detecting scheme is presented. Using the orthogonizable (7,3) cyclic code, double-failure-detecting count logic is accomplished in addition to single-failure-tolerant count logic. The proposed techniques can be applied in principle to other sequential circuits to increase its reliability.

耐障害 IC 記憶裝置 設計에 關하여

孫潤求 嶺南大學校 工業技術硏究所 1977 연구보고 Vol.5 No.1

Memories are one modular of Computer systems that are largely iterative. Specifically in the case of real-time operation, it is difficult to replace bad elements with good one. Under such conditions, the use of error correcting code may be desirable. Therefor, in this paper, (7,3) cyclic code is used. The problem of making a memory of W words, each 16 bit long, using semiconductor LSI. One reasonable partitioning is to build the equivalent of a core memory bit plane, complete with all associated circuitry, including address decoding, on one wafer. An 8-bit memory unit is a common subunit for modern computers. A parity check bit is added on a 1 Byte. The 9 bits(8 bit+1 parity check bit)are broken into subgroups of 3, then 7 bit (3 data bit+4 redundant bits) of storage can be used in a single error correcting double error detecting arrangement to store 3 data bits. Consequently a single error correction in a section is equivalent of multiple error correction in a word. In the case of error detection is also same as above mentioned

Seqence Generator의 신뢰성 향상을 위한 冗長技術 利用

孫潤求 嶺南大學校 工業技術硏究所 1980 연구보고 Vol.8 No.1

Recently the facts are recognized that even the α-ray or can cause the failure on VLSI chip, So the sequential circuits must have certain redundant circuits in order to be capable of correcting error. For this reason (7.3) Cyclic code is taken into consideration. In this paper a synthesis procedure for realizing a single failure-tolerant sequence generator with double-error self-detecting scheme using orthogonizable (7.3) cyclic code are presented.

한국어 음성분석을 통한 간이전화 다중전송의 가능성에 관하여

이무영,손윤구 嶺南大學校 工業技術硏究所 1974 연구보고 Vol.2 No.1

Through experimental analysis of the frequency vs intelligibility of korean speech, best combination of narrow bands could be selected, which enables to multiplex two channels of telephone communication with negligible loss in intellibilty. With a two narrow bands combination, ie. 0.3-0.5/1.2-1.8 KHz for channel 1 and 0.6-1.0/2.0-3.0 KHz for channel 2, total intelligibility of 92% were achieved, which were suffcient for normal telephone conversation in local communication. The speech compression in time demension is also experimented. With interruption frequency of 15 Hz, more than 80% intelligibility could be obtained in case of korean speech.

Mini-Floppy Disk Drive 의 Handler 에 관한 硏究

李在己,孫潤求 嶺南大學校 工業技術硏究所 1982 연구보고 Vol.10 No.2

With the increasing popularity of microcomputer system, mini-floppy disk drive has been widely used for the input/output storge of the host system becaues of its high speed and a large capacity to the cost. In this paper, floppy disk drive (FDD) has been presented as I/O data storage which user can easily handle the desired data by merely pressing a function key. For this purpose, the author has developed a handler to meet the requirements of FDD such as timing delay. And also, variable block size and soft sectoring are controlled by this handler. Implementing the developed handler, the author has obtained satisfactory result.

구조화 어셈블러용 전처리기의 개발

손윤구,이규호 嶺南大學校 工業技術硏究所 1986 연구보고 Vol.14 No.1

In this paper, STA(structured assembler) is suggested and a preprocessor for it has developed. The designed statements follow LL(1) grammer for simple parsing. The preprocessor accepts CP/M's M80 macroassembler source codes containing the designed block-structured statements and then outputs pure assembler codes. From a number of testing, it's documentability as good as most high-level programming languages and the efficiency of codes resulting from optimization routine have certified.

8-이웃 연결값에 의한 병렬세선화 알고리즘

원남식,손윤구,Won, Nam-Sik,Son, Yoon-Koo 한국정보처리학회 1995 정보처리논문지 Vol.2 No.5

세선화 알고리즘은 문자 인식에서 인식율을 높이기 위한 매우 중요한 과정이 된다. 본 연구는 다양한 문자 인식에 적용 가능한 8-이웃 연결값을 이용한 병렬세선화 알고 리즘을 제안한다. 제안된 알고리즘의 특징은 병렬성 구현이 용이하며, 세선화된 결과 는 완전 8연결이 되고, 수치 정보로 표현된다. 특히 곡선 선분의 골격이 정확하게 표 현되므로 영문, 일어 등 곡선이 많은 문자에 더욱 적합함을 보인다. 성능 평가는 기준 골격선과 유사도 측정 방법에 의해 수행되었다. A thinning algorithm is a very important procedure in order to increase recognition rate in the character recognition. This paper is the study of a parallel thinning algorithm available for the recognition of various characters, and it proposes the parallel thinning algorithm using the 8-neighbors connectivity value. Characteristics of the proposed algorithm are easiness of implementation of parallelism, the result of thinning is perfectly-8 connectivity and represented by numeric information. The proposed algorithm is very suitable for characters having many curve segments such as English, Japanese etc. Performance evaluation was performed by the measure of similarity to reference skeleton.

B-ISDN 및 N-ISDN에서의 멀티미디어 서비스 연동

정연기,김영탁,손윤구,Jeong, Yeon-Gi,Kim, Yeong-Tak,Son, Yun-Gu 한국정보처리학회 1994 정보처리논문지 Vol.1 No.3

64 Kbit/s을 기반으로 하는 N-ISDN에서의 멀티미디어 서비스와 ATM을 기반으로 하는 B-ISDN에서의 멀티미티어 서비스 간의 연동방안을 제시한다. 먼저 멀티미디어 서비스 제공을 위한 프로토콜 기능구조를 분석하고, 멀티미디어 서비스 연동을 위한 각 프로토콜 계층 기능을 제시하며, 64 Kbit/N-ISDN에서의 멀티미디어 서비스 제공 구조를 살펴본다. 그리고 B-ISDN에서의 멀티미디어 서비스 제공을 위한 ATM 프로토콜 기능을 분석한다. 특히 B-ISDN에서의 4가지 서비스 유형에 대한 ATM 적응 계층 및 상 위 계층과의 정합기능을 분석한다. 64 Kbit/s N-ISDN간의 멀티미디어 서비스 연동을 위한 기능구조를 제안한다. 또한 멀티미디어 통신을 위한 각 미디어별 연결 특성에 따른 연결 설정 방안 및 연동 방안을 제시한다. Interworking architecture and scenarios are analyzed and proposed for seamless provision of multimedia services across 64 kbit/s-based N-ISDN and ATM-based B-ISDN. First, the functional architecture of multimedia service is analyzed, and the functions of each protocol layer are proposed. The architecture of multimedia services in N-ISDN is studied, and the functions of ATM protocol for multimedia services in B-ISDN are analyzed. We propose the interworking architecture of multimedia services across 64 kbit/s-based N-ISDN and ATM-based B-ISDN.

영상처리 : 8-이웃 연결값에 의한 병렬세선화 알고리즘

원남식(Won Nam Sik),손윤구(Son Yoon Koo) 한국정보처리학회 1995 정보처리학회논문지 Vol.2 No.5

세선화 알고리즘은 문자 인식에서 인식율을 높이기 위한 매우 중요한 과정이 된다. 본 연구는 다양한 문자 인식에 적용 가능한 8-이웃 연결값을 이용한 병렬세선화 알고리즘을 제안한다. 제안된 알고리즘의 특징은 병렬성 구현이 용이하며, 세선화된 결과는 완전 8연결이 되고, 수치 정보로 표현된다. 특히 곡선 선분의 골격이 정확하게 표현되므로 영문, 일어 등 곡선이 많은 문자에 더욱 적합함을 보인다. 성능 평가는 기준 골격선과의 유사도 측정 방법에 의해 수행되었다. A thinning algorithm is a very important procedure in order to increase recognition rate in the character recognition. This paper is the study of a parallel thinning algorithm avaliable for the recognition of various characters, and it proposes the parallel thinning algorithm using the 8-neighbors connectivity value. Characteristics of the proposed algorithm are easiness of implementation of parallelism, the result of thinning is perfectly-8 connectivity and represented by numeric information. The proposed algorithm is very suitable for characters having many curve segments such as English, Japanese etc. Performance evaluation was performed by the measure of similarity to reference skeleton.