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서동환(Donghwan Seo),강태엽(Tae Yeob Kang),민준기(Joonki Min),이강영(Kang Young Lee),구영권(Young Gwon Gu),이강영(Kang Yung Lee),양일영(Il Young Yang),홍정표(Jeong Pyo Hong),김성규(Sung Kyu Kim),유상우(Sang Woo Yu) 한국신뢰성학회 2019 신뢰성응용연구 Vol.19 No.2
Purpose: Nowadays, it is necessary to ensure that defense systems, which have become very complex and modernized, are highly reliable. To prove the reliability of defense systems, reliability demonstration tests are usually required. The present study develops a method to design reliability demonstration tests for missiles stored in ammunition igloos without maintenance. Methods: The procedure followed herein is as follows. (1) Analysis of operation environments and effective stresses; (2) classification of fault mechanisms and their causes; (3) derivation of an accelerated factor (AF); (4) design of an accelerated test. Results: The reliability target of the missile is B10 : 10 years. Conditions for the test plan are as follows: shape parameter = 1, number of samples = 5, AF = 48.544, and confidence level = 60%. Finally, the test period according to the designed accelerated test plan was 3,139 h. Conclusion: We proposed a method to design reliability demonstration tests for missiles in the development period. The results of this study are expected to contribute to the development of reliable missiles that can be stored for long periods.
마이크로 구조를 가지는 소수성 표면 위의 액체 유동에 대한 수치적 연구
서동환(Donghwan Seo),최지영(Jiyoung Choi),손기헌(Gihun Son) 대한기계학회 2009 대한기계학회 춘추학술대회 Vol.2009 No.11
Numerical simulation is performed for liquid flow on a micro-structured hydrophobic surface, where liquid slip occurs due to the gas existing between the surface structures. The liquid-gas interface is calculated by a level-set method which is improved by employing a sharp-interface technique for accurately enforcing the no-slip and contact angle conditions at the fluid-solid interface as well as the velocity and stress matching conditions at the liquid-gas interface. The numerical results show that the liquid flow and friction reduction depend strongly on the contact angle, the gas-solid area ratio and the geometric parameters of microstructure.
MIL-STD-810H 규격의 고온 외 7 개 분야 주요 변경사항 분석
서동환(Donghwan Seo),강태엽(Tae-yeob Kang),민준기(Joonki Min) 대한기계학회 2021 대한기계학회 춘추학술대회 Vol.2021 No.4
In this paper, we analyzed for the environmental test standard(MIL-STD-810H 501.7 High temperature, 502.7 Low temperature, 503.7 Temperature shock, 505.7 Solar radiation, 506.6 Rain, 507.6 Humidity, 509.7 Salt fog, 514.8 Vibration). In addition, we compared MIL-STD-810H with MIL-810G w/Change1. Finally, we explained the major changes of the standard eight test items such as high temperature.
CMOS Class-E 전력증폭기의 Cascode 구조에 대한 게이트바이어스 효과 분석
서동환(Donghwan Seo) 한국전자파학회 2017 한국전자파학회논문지 Vol.28 No.6
본 논문에서는 cascode 구조가 적용된 Class-E 스위칭 모드 CMOS 전력증폭기의 common-gate 트랜지스터 게이트 바이어스 효과에 대해 분석하였다. 게이트 바이어스 효과를 확인하기 위해서 전력증폭기의 DC 전력소모, 효율을 분석하였다. 분석 결과를 통해서 전력증폭기의 최고 효율을 보여주는 common-gate 트랜지스터의 게이트 바이어스가 일반적으로 사용하는 전력증폭기 전원 전압보다 낮음을 확인하였다. 트랜지스터의 게이트 바이어스가 계속 감소함에 따라 on-저항을 확인하여 커지고, 이에 따라 출력, 효율이 감소하는 것도 확인하였다. 이 두 가지 현상을 통해 게이트 바이어스가 스위칭모드 전력증폭기에 미치는 영향을 분석하였다. 이 분석을 증명하기 위해서 0.18 ㎛ RF CMOS 공정으로 1.9 ㎓ 스위칭모드 전력증폭기를 설계하였다. 앞에서 설명한 것처럼 전력증폭기의 최대 효율은 전력증폭기의 인가 전압(3.3 V)보다 낮은 2.5 V에서 확인할 수 있었다. 이 때 최고 출력은 29.1 ㏈m, 최고 효율은 31.5 %이다. 측정 결과를 통해서 스위칭모드 전력증폭기 common-gate 트랜지스터의 게이트 바이어스 효과를 실험적으로 확인하였다. In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 ㎓ switching mode power amplifier using 0.18 ㎛ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 ㏈m. From the measureed results, we successfully verified the analysis.
S-parameter의 변화를 유도하는 임피던스 변화 감지를 통한 전자회로의 결함검출회로
서동환(Donghwan Seo),강태엽(Tae-yeob Kang),유진호(Jinho Yoo),민준기(Joonki Min),박창근(Changkun Park) 한국전기전자학회 2021 전기전자학회논문지 Vol.25 No.4
본 논문에서는 고장예측진단 및 건전성 관리 기법(Prognostics and Health Management, PHM)을 적용하기 위해 해당 시스템 혹은 회로 내부에서 결함특성을 감지하고 예측할 수 있는 회로 구조를 제안하였다. 기존 연구에서 회로 결함의 진행에 따라, S-parameter 크기 최소값의 주파수가 변화하는 것을 확인하였다. 이러한 특성을 기존에는 네트워크 분석기(Network Analyzer)를 활용하여 측정하였으나, 본 연구에서는 같은 결함검출기법을 활용하더라도 큰 계측장비 없이 결함의 진행상황 및 잔여 수명, 결함발생 여부를 확인할 수 있는 소형화된 회로를 설계하였다. 본 연구에서는 S-parameter의 변화를 야기하는 임피던스의 변화를 감지할 수 있도록 회로를 설계하였으며, Bond-wire의 온도반복에 따른 S-parameter 변화 측정결과를 제안하는 회로에 적용하였다. 이를 통해 해당 회로가 Bond-wire의 결함을 감지할 수 있다는 것을 성공적으로 검증하였다. In this paper, in order to apply Prognostics and Health Management(PHM) to an electronic system or circuit, a circuit capable of detecting and predicting defect characteristics inside the system or circuit is implemented, and the results are described. In the previous study, we demonstrated that the frequency of the amplitude of S-parameter changed as the circuit defect progressed. These characteristics were measured by network analyser. but in this study, even if the same defect detection method is used, a circuit is proposed to check the progress of the defect, the remaining time, and the occurrence of the defect without large measurement devices. The circuit is designed to detect the change in impedance that generates changes of S-parameter, and it is verified through simulation using the measurement results of Bond-wires.
MIL-STD-810 환경시험조건을 이용한 무기체계 핵심구성품 온도/진동복합 정상수명시험 설계 방안
강태엽(Tae Yeob Kang),서동환(Donghwan Seo),민준기(Joonki Min),이강영(Kangyoung Lee),김성규(Sungkyu Kim),홍정표(Jeongpyo Hong),양일영(Ilyoung Yang),유상우(Sangwoo Yu) 한국신뢰성학회 2021 신뢰성응용연구 Vol.21 No.1
Purpose: Previous work regarding reliability testing has focused on accelerated life testing, leading to a lack of information on non-accelerated life testing; however, it is a proper choice when testing time is not a constraint. Methods: Therefore, the design process of the non-accelerated testing is proposed, including selecting the essential component to test, defining target life expectancy and main stress factors, designing testing profiles, and determining the number of test items and testing periods. Especially, this paper provides the guideline with which the stress levels and the test profile can be designed based on the MIL-STD-810 standard. Results: We show that the vibration testing profile can be designed by applying the Miner-Palmgren rule to the given MIL-STD-810 profile. The temperature range of interest was directly derived from the standard. Conclusion: This paper presents the design guideline of the non-accelerated life testing case where the test item is an essential component of defense systems and the main stress factors are temperature and vibration.