http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
변상봉(Sang-Bong Byun),이용환(Yong-Hwan Lee) 한국정보기술학회 2009 Proceedings of KIIT Conference Vol.2009 No.-
기존의 디바이스간 저속 병렬연결 방식은 가격, 전력소모, EMI, 부피 등 많은 단점이 있다. 이러한 단점을 보완한 직렬 인터페이스의 표준인 MIPI(Mobile Industry Processor Interface)[1]가 새로운 인터페이스로 각광받고 있다. 기존의 직렬 인터페이스는 점대 점 연결방식으로 많은 디바이스들이 장착되는 환경에서는 복잡도 증가와 효율성 저하가 발생한다. 그리하여 고속 데이터 전달을 위한 링크 스위치를 사용하여, 모바일 환경에서 다양한 디바이스들 간의 통신이 패킷 스위칭 방식으로 효율적으로 이루어질 수 있도록 한다. Low-speed parallel interface has many shortcomings. The shortcomings are price, power consumption, EMI, bulky dimension. To compensate for these shortcomings, the standard serial interface MIPI(Mobile Industry Processor Interface)[1] has been prominent as a new standard. Existing serial interface using a point to point connection, if it is used in complex system, shows decreased efficiency and increased complexity. Therefore we will using the link switch for high speed data transmission protocol so that communication between various devices in the mobile environment performed by packet switching.
모바일 기기내의 효율적인 데이터 전송을 위한 고속 스위치 설계
변상봉(Sang-Bong Byun),이용환(Yong-Hwan Lee) 한국정보기술학회 2013 한국정보기술학회논문지 Vol.11 No.2
Smart phones that provide various functions should integrate a variety of chips and devices. Direct connections between various devices need many lines, which result in the increment in volume and the decrement of transmission speed, noise and reliability. In this paper, a design of switch for supporting fast serial interface is presented. The switch has high compatibility using Data Link Layer and Network Layer of OSI 7 layers and can efficiently arbitrate data transmissions between multiple devices. The switch also supports a priority scheme in determining the transmission order according to the requested transmission speeds and improves the integrity of data transmission by detecting error using CRC(Cyclic Redundancy Check) code. The hardware design is verified through FPGA and chip implementation.
변상봉(Sang-Bong Byun),문병인(Byungin Moon),이용환(Yong-Hwan Lee) 한국정보기술학회 2010 한국정보기술학회논문지 Vol.8 No.11
Various multimedia features are widely adopted for high performance mobile devices. Accordingly, fast serial interface with the feature of high-speed operation and low power consumption but small chip area is attractive. Serial interface is being standardized to accomodate various chips in an unified high-speed transmission topology. In addition, the efficiency of data transmission is required for the different priorities. In this paper, based on the layer structure of the PCI (Peripheral Component Interconnect) Express, a low-power general interface for fast data transfer is implemented. In this design, compatibility was improved by using the OSI 7 layers and low power operation was available by a power management unit. The hardware design was verified through FPGA and chip implementations.