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김석준(Kim Sug-Jun) 한국시학회 2008 한국시학연구 Vol.- No.21
In this treatise, I was inquired into Kim Kwang-kyun's poetics and the Fusion of Horizon. In the established research, the valuations of Kim Kwang-kyun' poetry tend to be decided into the negative appraisal due to the heterogeneous combination of sentimentalism and pictorialness. And then this research displays the difference and the discrepancy between poetics and poetry; the combination of sentimentalism and pictorialness correspond to the appearance of new style, what is called Romantic Imagism or Imagistic Romanticism. That displays the type of the fusion of horizon in order to create the new horizon This treatise hypothesizes that Kim Kwang-kyun's poetic essence is solitude and grief, and explains to their conscious strata. The solitude and grief are those days' social reality and collective unconsciousness. Further The solitude and grief are due to forming poetic self which is depressed mood because of his biographic fact(family's death : father and sister). Therefore Kim Kwang-kyun's poetic practice combine the 1920' romantic tendency with the 1930' imagism, which means to enhance individuality to speciality in order to accomplish Kim's personality
리프팅 기반의 고속 정수 웨이블릿 변환의 효율적인 구현 구조
김석준,장영조,Kim, Suc June,Jang, Young Jo 대한임베디드공학회 2012 대한임베디드공학회논문지 Vol.7 No.4
In this paper, we propose an efficient architecture for 2D IWT using an existing 1D IWT. Lifting based IWT is the architecture of which a multiplier is replaced by adders and shift registers. The structure is relatively simple and modular. The proposed architecture to process an image size with 256x256 pixels consists of 16 adders, 8 shift registers, and some memories. By processing two rows at the same time, 2D sub-band coefficients can be calculated immediately after 1D sub-band coefficients have been processed. The architecture is designed so that each image can be inputted consecutively. The number of adders and shift registers is increased by twice comparing the existing architecture, but the memory size and the execution time are decreased by half. The proposed architecture is implemented using Verilog-HDL and simulated using iSim. It is synthesized and demonstrated at ISE for xc5vlx330 in RPS3K board.