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RISS 인기검색어
- 검색키워드
- 저자 : Yeonghun Kim (검색결과 3 건)
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Yeonghun Kim Graduate school of UNIST 2014 국내석사
To be successful in the market, industries have kept trying to introduce new products that satisfy users’ expectations. Under this circumstance, companies have realized and emphasized the importance of collaborative environment where different team members closely work together to meet the diverse expectations of the users. Many practitioners and researchers believe that high-level cross-functional integration can create an advantage of better product quality and shorter development time. However, although the collaborative teams have been developed with great optimism, it seems that diverse team members have confronted inevitable conflicts each other, and this often resulted in a big loss of company revenues considering the development time and cost. Based on the current situations, this research was focused on figuring out barriers within collaborative product development teams and developing a practical tool that can help improve the collaborative works between different team members. In order to understand current barriers in collaborative product development teams, literature review was first conducted and this was followed by a semi-structured interview with six designers. In the literature, different thought world, team disagreement, fairness, and team organization form were mainly mentioned as the main causes of conflicts, and, in the interview with designers, five common causes of conflicts were identified; different communication tools, different personality and preferences, political issues, lack of manager’s leadership, and separated working space. Most causes of conflicts between designers, engineers, and marketers were similarly found between the literature review and the interviews. However, newly emerging conflicts within different designers were also discovered according to the results of the interviews. This seems because that the designer’s area has been getting broaden and specialized. Especially, many conflicts occurred between product and UX designers by their duplicated work areas and prejudice. Based on the results, an idea workshop for developing a collaborative tool was carried out with graduate students studying industrial design. Finally, a collaborative toolkit was developed into two different ways. One is a conversation tool through which every team member including designers, managers, marketers, and engineers can start to discuss the conflicts within their team and come up with solutions for effective collaborative works, and the other is a common sense tool for creating and sharing common sense between product and UX designers. An expert interview and a focus group interview were followed to see the effectiveness and usability of the toolkit as final output.
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Design of power management unit for transmitter pulser with digital controller
Kim, Yeonghun Sungkyunkwan University 2023 국내석사
본 논문에서는 TSMC 130nm 공정 기술로 Digital Controller를 이용한 5kHz~5MHz의 주파수를 갖는 Pulse 신호 기반의 High Voltage Tx Pulser 및 이를 구동하기 위한 Power Management Unit 회로를 제안한다. Multi-Channel Transducer array 구동을 위한 High Voltage Pulser로 신뢰성 높은 Ultrasound Imaging 송신 (Tx)이 가능하며, 선형적인 DC 전원을 제공해주는 안정적인 Power Management Unit 회로가 요구된다. Digital Controller는 20MHz의 동작 주파수를 가지며, Serial 통신 방식 중 하나인 SPI (Serial Peripheral Interface)를 이용하여 16MHz Clock 기반으로 데이터를 송수신한다. 또한, 5kHz~5MHz의 Pulse 신호의 주파수를 10kHz 단위로 구분하여 원하는 대역을 선택할 수 있다. Pulse 한 주기 내의 High 신호 구간 비율인 Duty Ratio를 조절하여 선택한 주파수를 유지하며 Pulse Width의 비율을 50~90%로 조절할 수 있다. 12V의 DC-DC Boost Converter로 전원을 받는 High Voltage Pulser에서 동작하기 위해 Digital 전압으로 출력되는 Pulse 신호를 Level Shifter로 외부 입력 전원으로 전압 승압 후 Driver 구조를 통하여 12V로 Pulse 신호 유지가 가능하다. Power Management Unit 회로는 외부 입력 전원 인가 후 Enable 신호가 없는 Always on block이 처음으로 동작하며, Digital Controller block과 내부 Digital Domain에 1.5V의 전원을 공급한다. Start up 회로와 입력 전원에 무관한 BMR (Beta Multiplier Reference) 구조 기반으로 PNP BJT를 사용한 1.2V BGR과 Current Mirror OTA Error Amplifier 구조 기반의 1.5V LDO로 구성되어 있다. Digital Controller로 공급하는 BGR과 LDO의 경우 각각 nW급 저전력의 성능을 가진다. Always on block 안정화 후 Enable 신호를 조절하여 1.2V BGR 전압을 입력 전압으로 받는 p-type 2-Stage Op-Amp 구조 기반으로 Negative Feedback Loop를 형성하는 Buffer를 통한 전압을 Dividing 후 460mV BGR과 1.13V BGR이 동작한다. 각각의 BGR은 AFE, ADC, TRx block에 1.5V 전원을 공급하기 위한 LDO와 DC-DC Converter block에 3V 전원을 공급하기 위한 LDO의 입력 전압으로 인가된다. This study proposes a pulse signal-based high voltage Tx pulser with a frequency of 5 kHz to 5 MHz using a digital controller and power management unit in 130 nm process technology. High voltage pulser for multi-channel transducer array operation enables reliable ultrasound imaging transmission (Tx), and requires a stable power management unit circuit that provides linear DC power. The digital controller has an operating frequency of 20 MHz. Serial peripheral interface (SPI), one of the serial communication methods, transmits and receives data based on a 16 MHz clock. In addition, it selects a band to be used by dividing the frequency of a pulse signal of 5 kHz to 5 MHz in 10 kHz units. By adjusting the duty ratio, which is the ratio of the high signal section within a pulse period, the selected frequency can be maintained, and the pulse width ratio can be adjusted from 50% to 90%. To operate in a high voltage pulser powered by a DC-DC boost converter of 12 V, a pulse signal output at a digital voltage is boosted to an external input power source with a level shifter. A driver structure maintains a pulse signal at 12 V. In the power management unit circuit, the always on block without an enable signal operates for the first time after external input power is applied, and supplies 1.5 V power to the digital controller block and the internal digital domain. It comprises a 1.2 V bandgap reference (BGR) using PNP BJT element based on a beta multiplier reference (BMR) structure independent of input power and startup circuit, and 1.5 V low dropout (LDO) based on current mirror OTA error amplifier structure. In the case of BGR and LDO supplied to the digital controller, each has nW-class low power performance. Buffer based on the p-type 2-Stage op-amp structure that receives 1.2 V BGR as input voltage by adjusting the enable signal after always on block stabilization, 460 mV BGR, and 1.13 V BGR after dividing the voltage. Each BGR is applied as an input voltage of LDO for supplying 1.5 V power to the AFE, ADC, and TRx block and LDO for supplying 3 V power to the DC-DC converter block.
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