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RISS 인기검색어
- 검색키워드
- 저자 : Das, Sudeep (검색결과 170 건)
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Application-aware on-chip networks
Das, Reetuparna The Pennsylvania State University 2010 해외박사(DDOD)
Multi-hop packet-based Network-on-Chip (NoC) architectures are widely viewed as the de facto solution for integrating the nodes in many-core architecture for their scalability and well-controlled and highly predictable electrical properties. The Network-on-Chip (NoC) has become an important research focus in recent years because the network plays a critical role in determining the performance and power behavior of a many-core architectures. Most of the innovative solutions proposed for NoC research problems focus on independently optimizing the NoC without exploiting characteristics of applications or software stack. This thesis offers a unique perspective of designing high-performance, scalable and energy efficient NoC's by utilizing application characteristics. In this thesis, I show that we can design much superior on-chip networks if we understand application behavior and customize on-chip networks for them. I propose application-aware approaches for packet scheduling in on-chip networks, application communication locality aware hierarchical topologies for NoCs, and data compression techniques which exploit value locality inherent in application data traffic. The first contribution of this thesis is to devise application-aware packet scheduling policies for NoCs. The NoCs are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple applications to efficiently and fairly share the network, to improve system performance. A key component of a router that can influence application-level performance and fairness is the arbitration/scheduling unit. Existing polices for arbitration and packet scheduling in NoCs are local and application oblivious. However, we observe that different application characteristics can lead to differential criticality of packets: some packets will be more important to processor execution time than other packets. This novel insight enables us to design packet scheduling polices to provide high performance in on-chip networks. First, I propose a coordinated application-aware prioritization substrate. The idea is to divide processor execution time into phases, rank applications based on the criticality of network on each applications performance (or based on system-level application priorities) within a phase, and have all routers in the network prioritize packets based on their applications ranks in a coordinated fashion. Our scheme includes techniques that ensure starvation freedom and enable the enforcement of system-level application priorities, resulting in a configurable substrate that enables application-aware prioritization in on-chip networks. Next, I propose a new architecture Aergia, to exploit slack in packet latency. In this thesis, we define slack as a key measure that characterizes the relative importance of a packet. Specifically, the slack of a packet is the number of cycles the packet can be delayed in the network with no effect on execution time. We propose new router prioritization policies that exploit the available slack of interfering packets in order to accelerate performance-critical packets and thus improve overall system performance. When two packets interfere with each other in a router, the packet with the lower slack value is prioritized. I describe mechanisms to estimate slack, prevent starvation, and combine slack-based prioritization with the application-aware prioritization mechanisms proposed above. The second contribution of this thesis is application-aware hierarchical topologies. This proposal leverages the insight that applications mapped on a large CMP system will benefit from clustered communication, where data is placed in cache banks closer to the cores accessing it. Thus, we design a hierarchical network topology that takes advantage of such communication locality. The two-tier hierarchical topology consists of local networks that are connected via a global network. The local network is a simple, high-bandwidth, low-power shared bus fabric, and the global network is a low-radix mesh. Since most communication in CMP applications can be limited to the local network, using a fast, low-power bus to handle local communication will improve both network latency and power-efficiency. The final contribution of this thesis is data compression techniques for on-chip networks. In this context, we examine two different configurations that explore combinations of storage and communication compression: (1) Cache Compression (CC) and (2) Compression in the NIC (NC). We also address techniques to hide the decompression latency by overlapping it with communication latency. We comprehensively characterize and quantify in detail the effect of data compression on NoCs. The attractive benefits seen from our evaluations make a strong case for utilizing compression for optimizing the performance and power envelope of NoC architectures. I also take advantage of compressibility of application data traffic to improve the throughput via novel router microarchitecture, called XShare. The XShare architecture utilizes data value locality and bimodal traffic characteristics of CMP applications to transfer multiple small flits over a single channel.
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A Study of new IMV circuit using pressure feedback and energy saving
Debdatta, Das 울산대학교 대학원 2016 국내석사
Fluid power technology is widely used in industal porpose for its high power to size ratio. They are used in a large scale in excavation, construction and agriculture systems. However, its energy efficiency became a big concern in the recent years. As a result, a noticeable progress is seen to improve fluid power energy efficiency from many aspects. This thesis mainly focuses on hydraulic actuation system. In recent research on hydraulic system is mainly focusing on energy saving because the efficiency of the hydraulic system is very low even though it has large power to size ratio. In mobile hydraulic equipment, conventional hydraulic spool valves with pressure compensator are already replaced by valve assemblies with four valve independent metering with electronically controlled pressure compensation. The independent metering concept and microprocessor control have a huge potential of saving more energy than the conventional proportional valve control because of the increased controllability of the system. The primary focus of this study to reduce the number of independent metering valve (IMV) by introducing one directional control valve. This new model offers two degrees of freedom i.e. controlling velocity and pressures same as conventional IMV. In the system described here, two of the three independent valves are active during metering. The theory behind a new method of flow control based upon pressure feedback is presented for two of the five distinct metering modes and the performance is investigated with respect to conventional IMV configuration. Later on, details mathematical modeling for each working mode is developed. After that, Simulation has been done to invistagete the system performance in comparison with CIMV configuration. Simulation results show that the performance is much better than the conventional IMV system and can save more energy.
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Sajib, Das 인하대학교 대학원 2021 국내석사
Fintech has become the focus of considerable attention for money transfer companies. To provide service smoothly and fast, they are significantly using Fintech. It is essential to understand better why users are willing to adopt Fintech. Some positive and negative factors are playing a role in adopting Fintech by users. In this research, I have used the Technology Acceptance Model (TAM) to prove the adoption. The model has been examined based on the empirical data collection from 115 Fintech users. I have analyzed the data with confirmatory factor analysis (CFA). The number of parameters was 48. The result for the comparative fit index (CFI) is 0.946, and Root means the square error of approximation (RMSEA) is 0.046. P-value (Chi-square) is 0.063 for the model test user model, and the p-value is 0.000 for the model test baseline model.
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Advertisement-based demand-response management in smart grids
Das, Sumana Sungkyunkwan University 2014 국내석사
It has been decades since the installation of our electric grids. The present electric power system structure has lasted for decades; it is still partially proprietary, energy-inefficient, physically and virtually (or cyber) insecure, as well as prone to power transmission congestion and consequent failures. To make today’s electricity grid smarter, one have to effectively regulate energy usage by exploiting the prospectively installed wireless communication system, Automatic meter reading, Smart meter infrastructure (AMI), and Demand response (DR) management programs. Advanced distribution automation and dynamic pricing scheme also plays a significant role to achieve this goal. In this thesis, the author proposes an incentive based pricing model. It empower consumers to be part of decision makers and alongside the electricity suppliers, consumers also play a vital role in saving energy. Eventually it will help them to be responsible energy users. In this, we try to study the past energy usage data to meet the present days real time energy demands. The suggested scheme also provides a solution to overcome peak loads and over consumption of power leading to huge blackouts by involving both utilities and consumers.
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Das, Mousumi Handong Global University 2006 국내박사
The trend to higher integration and higher transmission speed challenges modeling engineers to develop accurate device models up to GHz range. An absolute prerequisite for achieving this goal are reliable measurements that have to be checked for data consistency and plausibility and accurate physics based model equation. This paper possesses a scalable large signal model for deep submicron MOSFET s capable of accurate DC and RF simulation for different biasing conditions. It studies the behavior of different devices developed with 0.25 μm CMOS. At first a non-scalable Model which is accurate only in saturation regime is presented. The Model equation based on physics and some empirical fitted parameters are introduced to provide better accuracy. The proposed channel current equation satisfy sub-threshold to strong inversion region without any discontinuity, and the nonlinear intrinsic capacitors, Cgs and Cgd are described to smooth equations within the bias range 2.5V < VGS and 2.5V < VDS. The Model is implemented in SDD package in ADS and due to simplicity of nonlinear equations it shows good convergence in HB simulation. An amplifier is designed and tested at 915 MHz to check the accuracy of the proposed model. The developed model predicts well power gain and P1dB performance and also measured third order intermodulation agrees well with simulation result up to P1dB power level. The channel current equation of the model is then modified to predict the behavior of I-V curve linear as well in saturation regime and the DC model with parasitic are then scaled down with width and fingers. DC scaling mainly consider effects of threshold voltage , mobility, drain induced barrier lowering ,channel length modulation and knee voltage variation . AC scaling consider effect of gate resistance, drain and source resistances, parasitic capacitances including nonlinear capacitances Cgs & Cgd . The RF performance of the model is checked by making it as a Colpitt oscillator of oscillation frequency 1 GHz and verifying it through the measured device of Hynix 0.25 μm process. Its result in comparison with numerical device simulations and measurements show good agreement to the dimension of 0.25 μm.
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